1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a self-aligned contact (SAC) window.
2. Description of the Related Art
As the dimensions of size approach 0.25 .mu.m or less, the etching process for the contact becomes difficult due to the design rule and limitation of exposure light resolution. Therefore, a self-aligned contact process is developed. The principle of the self-aligned process is to use an etching recipe that is highly selective to two different dielectrics, such as silicon oxide and silicon nitride, during the etching process for the contact, so that the design rule can be relaxed.
Generally, the dielectrics covering the devices is silicon oxide so that silicon nitride is used as an etching stop for the self-aligned contact. Therefore, a recipe with high oxide but low silicon nitride etching rate has to be adjusted.
BPSG with a high dopant is used as a dielectrics and since it is flowable during thermal process, a planarized surface can be provided for the wafer having a device structure thereon. Accordingly, BPSG becomes the preferred planarization dielectrics. However, the BPSG having dopants such as phosphorus and boron inside leads to a higher etching rate than non-doped silicon oxide, which causes it to be easily eroded in a solution by wet etching. As a result, the features of BPSG, such as its highly doped state and easy reflow ability, often cause short circuits during the subsequent cleaning processes. Therefore, BPSC is not suitable as an inter-dielectric for complex and tight design rule IC products, such as DRAM devices.